In synchronous system memories, an external clock signal drives individual synchronous memory devices in the system, and the synchronous memory devices perform specific data transfer operations, typically in response to the rising edges of the external clock signal. For example, in a typical synchronous dynamic random access memory ("SDRAM") a processor or some other external circuit applies address, data and transfer command information to one of the SDRAMs. The SDRAM latches the address and command information on a particular rising edge of the external clock signal, and the processor knows that a predetermined number of clock cycles later data may be read from the addressed SDRAM. During such data transfers, a clock buffer circuit in the SDRAM develops an internal clock signal in response to the external clock signal, and the various components within the SDRAM are controlled in response to the internal clock signal. The clock buffer circuit typically includes a one-shot circuit which operates to develop the internal clock signal in response to the external clock signal. In modern system memories, the frequency of the external clock signal is ever increasing to enable data transfer to and from the SDRAMs at correspondingly faster rates. As the external clock frequency increases, operation of the one-shot circuit becomes more critical due to the corresponding frequency increase of the internal clock signal that must be developed by the one-shot circuit.
FIG. 1 illustrates a conventional clock buffer circuit 10 including an input buffer circuit 12 receiving an external clock signal XCLK supplied by an external circuit (not shown in FIG. 1). The buffer circuit 12 inverts the external clock signal XCLK and develops an inverted clock signal XCLK on an output. The clock buffer circuit 10 further includes a one-shot circuit 38 receiving the inverted external clock signal XCLK, and developing a pair of complementary internal clock signals CLKIN and CLKIN in response to the clock signal XCLK. The one-shot circuit 38 includes a pair of cross-coupled NAND gates 40 and 42 connected as shown to form an RS flip-flop 44, as known in the art. A NAND gate 46 provides on its output a reset pulse in response to a high signal at the output of the NAND gate 40, and a high output from a delay circuit 48. The delay circuit 48 develops a high output a predetermined time after the clock signal CLKIN goes high. The reset pulse signal on the output of the NAND gate 46 is coupled to one input of the NAND gate 42, and operates to reset the RS flip-flop 44, as will be described in more detail below. Although the one-shot circuit 38 is shown as directly developing the internal clock signals CLKIN and CLKIN, one skilled in the art will appreciate a conventional driver circuit (not shown in FIG. 1) may be coupled to the outputs of the RS flip-flop 44. Such a conventional driver circuit develops the internal clock signals CLKIN and CLKIN in response to the outputs from the flip-flop 44, and may be utilized to ensure such internal clock signals have very sharp rising and falling edges.
The delay circuit 48 includes two positive-edge delay circuits 50 and 52 connected in series as shown, each operable to delay for a delay time t.sub.d a rising edge on their inputs, and to pass without such a delay a falling edge on their inputs. FIG. 2 is a more detailed schematic of the positive-edge delay circuits 50 and 52 comprising the delay circuit 48. The positive-edge delay circuit 50 includes a NAND gate 54 having inputs receiving the signal CLKIN and the supply voltage V.sub.CC, respectively, and an output coupled to a node D1'. The NAND gate 54 is typically formed of NMOS and PMOS transistors (not shown) which are sized such that the transistors driving the output high are relatively large while the transistors driving the output low are relatively small, thereby causing the NAND gate 54 to drive the node D1' high relatively quickly and low more slowly. A capacitor 56 is coupled between the node D1' and ground, and has a value selected to define the delay time t.sub.d of the positive-edge delay circuit 50. An inverter 58 drives the output D1 high when the voltage on node D1' drops below a low threshold voltage, and drives the output D1 low when the voltage on node D1' exceeds a high threshold voltage. The positive-edge delay circuit 52 includes a NAND gate 60, a capacitor 62, an inverter 64, an internal node D2' and an output D2 coupled as shown, and each of which operates in the same manner as previously described for the positive-edge delay circuit 50.
This series connection of the positive-edge delay circuits 50 and 52 results in the delay times t.sub.d of the two circuits being summed together with the output D2 going high two predetermined time delays t.sub.d after the signal CLKIN goes high. Although the delay times t.sub.d of the positive-edge circuits 50 and 52 are described as being equal, one skilled in the art will realize that in other embodiments the delay times t.sub.d may be different.
The operation of the clock buffer circuit 10 will now be described in more detail with reference to the timing diagram of FIG. 3. It should be noted that the signal CLKIN is not shown in the timing diagram of FIG. 3, but one skilled in the art will understand that this signal is merely the complement of the signal CLKIN. The clock buffer circuit 10 may be viewed as operating in one of three modes. In a first mode, designated a positive-edge mode, the clock buffer circuit 10 drives the internal clock signals CLKIN and CLKIN high and low, respectively, in response to a rising edge of the external clock signal XCLK. In a delay mode, the clock buffer circuit 10 times a delay time. After expiration of the delay time, the clock buffer circuit 10 commences the third mode of operation, designated the reset and precharge mode. During the reset and precharge mode, the clock buffer circuit 10 drives the clock signals CLKIN and CLKIN low and high, respectively, and precharges the circuits 50 and 52 in anticipation of the next rising edge of the external clock signal XCLK. Each of these modes will be described in more detail with reference to the timing diagram of FIG. 3.
Before a time t.sub.0, the signals XCLK, D1, D2, and CLKIN are low, while the signals on nodes D1', D2', and the output of the NAND gate 46 are high. At the time t.sub.0, the external clock signal XCLK goes high and the clock buffer circuit 10 operates in the positive-edge mode. In response to the external clock signal XCLK going high, the buffer 12 drives the inverted clock signal XCLK low. When the signal XCLK goes low, the NAND gate 40 drives the internal clock signal CLKIN high at a time t.sub.1.
When the internal clock signal CLKIN goes high, the delay mode of operation commences. In the delay mode, the positive-edge delay circuit 50 begins timing the delay time t.sub.d in response to the signal CLKIN going high. In other words, when the signal CLKIN goes high, the NAND gate 54 drives its output low which starts discharging the capacitor 56 as indicated by the decay of the voltage on the node D1' at the time t.sub.1. At about a time t.sub.2, the inverter 58 drives the output D1 high in response to the voltage on node D1' dropping below the low threshold voltage of the inverter. As indicated in the timing diagram, the output D1 goes high the delay time t.sub.d after the signal CLKIN goes high. When the output D1 goes high at time t.sub.2, both inputs of the NAND gate 60 of the positive-edge delay circuit 52 are high, causing the NAND gate 60 to drive its output low which begins discharging the capacitor 62 as indicated by the decay of the voltage on node D2'. The output D2 of the positive-edge delay circuit 52 remains low until the voltage on the node D2' is discharged below the low threshold voltage of the inverter 64. At a time t.sub.3, the inverter 64 drives the output D2 high in response to the voltage on node D2' dropping below the low threshold voltage of the inverter. Note that just before the time t.sub.3, the external clock signal XCLK goes low causing the buffer circuit 12 to drive the signal XCLK high. At this point, even though the signal XCLK goes high, the output of the NAND gate 40 continues driving the signal CLKIN high because the output of the NAND gate 42 remains low.
When the output D2 goes high at time t.sub.3, the reset and precharge mode of operation commences. In response to the output D2 going high, the NAND gate 46 drives its output low since both its inputs, D2 and CLKIN, are high. The output of the NAND gate 46 functions as a reset signal for the RS-flip-flop 44, and when its output goes low the internal clock signals CLKIN and CLKIN are reset low and high, respectively, in anticipation of the next rising edge of the external clock signal XCLK. More specifically, at the time t.sub.4, the low output from the NAND gate 46 causes the NAND gate 42 to drive its output high. In response to the output of the NAND gate 42 going high, the NAND gate 40, which now has two high inputs, drives the signal CLKIN low at time t.sub.4. In this way, the output of the NAND gate 46 operates as a reset pulse to drive the signals CLKIN and CLKIN low and high, respectively.
When the signal CLKIN goes low at time t.sub.4, the precharging portion of the reset and precharge mode begins. During the precharge portion, the output of the NAND gate 46 goes high just after the time t.sub.4 in response to the signal CLKIN going low. In addition, the low signal CLKIN causes the positive-edge delay circuits 50 and 52 to begin precharging their respective internal nodes D1' and D2' as indicated by the increasing voltages on these nodes just after the time t.sub.4. A short time after the time t.sub.4, the inverter 64 drives the output D2 low in response to the voltage on node D2' exceeding the high threshold voltage of the inverter 64. At approximately the same time, the inverter 58 drives the output D1 low in response to the voltage on node D1' exceeding the high threshold voltage of the inverter 58.
After the time t.sub.4, the voltages on nodes D1' and D2' continue to increase as these nodes precharge. A precharge time is defined for the positive-edge delay circuits 50 and 52 as the time between when the respective internal nodes D1' and D2' begin precharging to when the nodes begin discharging. Accordingly, a precharge time t.sub.p50 of the positive-edge delay circuit 50 is from the time t.sub.4 to a time t.sub.5, and a precharge time t.sub.p52 of the positive-edge delay circuit 52 is from the time t.sub.4 to a time t.sub.6. The precharge time t.sub.p52 is longer than the precharge time t.sub.p50 so the positive-edge delay circuit 52 has longer to precharge the internal node D2' than the positive-edge delay circuit 50 has to precharge the internal node D1'. The positive-edge delay circuit 52 is able to fully precharge the node D2' due in part to the longer precharge time t.sub.p52, and in part because the node D2' was not discharged as close to ground when precharging began at time t.sub.4.
At the time t.sub.5, a second cycle of the external clock signal XCLK is marked by the signal XCLK going high, and the clock buffer circuit 10 once again begins operation in the positive-edge mode. As previously described, when the signal XCLK goes high the signal CLKIN goes high a short time later, causing the delay circuit 50 to begin discharging the node D1' during operation in the delay mode. From the timing diagram, it is seen that at the time t.sub.5 the voltage on node D1' has not yet been fully precharged to the supply voltage V.sub.CC. As a result, when the capacitor 56 starts discharging at just after time t.sub.5, the voltage on the node D1' reaches the low threshold voltage of the inverter 58 faster than it did in the previous cycle. This is true because the voltage on node D1' must be discharged from a lesser voltage than in the previous cycle at just after the time t.sub.0. At a time t.sub.6, the output D1 goes high upon the voltage on node D1' reaching the low threshold voltage of the inverter 58. The delay time of the positive-edge delay circuit 50 during this cycle is given by the time interval from just after time t.sub.5 to time t.sub.6, and is designated t'.sub.d. The delay time t'.sub.d is seen to be shorter than the delay time t.sub.d during the last cycle. Thus, the output D1 goes high sooner than is desired due to the delay circuit 50 not having been fully precharged before the positive-edge of the signal XCLK at time t.sub.5. In response to the output D1 going high at time t.sub.6, the clock buffer circuit 10 operates as previously described with the output D2 going high at a time t.sub.7 and the signal CLKIN going low a short time later at a time t.sub.8.
The shorter delay time t'.sub.d of the positive-edge delay circuit 50 manifests itself as a variation in the pulse width of the internal clock signals CLKIN and CLKIN. The internal clock signal CLKIN has a shorter pulse width t'.sub.w for its second pulse between times t.sub.5 and t.sub.8 than its initial pulse width t.sub.w between times t.sub.1 and t.sub.4. The shorter pulse width t'.sub.w of the second pulse is due to the shorter delay time t'.sub.d of the positive-edge delay circuit 50 caused by the node D1' not having time to fully precharge to its desired level. As shown in the signal timing diagram, a third pulse of the internal clock signal CLKIN may have yet a different pulse width t".sub.w due to the varying precharge voltage on node D1'. Thus, the pulse width of the internal clock signal CLKIN varies undesirably during operation of the clock buffer circuit 10 due to the variations in the delay time of the positive-edge delay circuit 50 caused by the inability to precharge the internal node D1' during the precharge time t.sub.p50 available at the operating frequency of the external clock signal XCLK. As the frequency of the external clock signal XCLK increases, the precharge time t.sub.p50 available to fully precharge the internal node D1' decreases, and variations in the pulse width of the signal CLKIN from cycle to cycle become more significant. Although the positive-edge delay circuit 52 is described as fully precharging the internal node D2', similar problems may result for the circuit 52 as the frequency of the external clock signal XCLK increases and the precharge time t.sub.p52 accordingly decreases.
There is a need for a one-shot circuit having a delay circuit capable of a fast precharge to thereby enable the one-shot circuit to develop an internal clock signal having a constant pulse width in response to a high frequency external clock signal.